1. Field of Invention
The invention relates to a cyclic pipeline analog to digital converter, and more particularly to a cyclic pipeline analog to digital converter with highly enhanced accuracy.
2. Related Art
Analog to digital converters have been widely used in various digital electrical products, such as digital cameras, digital voice recorders, and the like. In the conventional converters, the pipeline analog to digital converter and the cyclic pipeline analog to digital converter are frequently used now.
Referring to FIG. 1, the pipeline analog to digital converter 1 includes a sample/hold module 11, a converting module 12 and a delay digital correction module 13. The sample/hold module 11 samples an input signal 111 and then generates a sample signal 112. The converting module 12 includes N-th stages of sub-converting units 121 to 129. The first stage of sub-converting unit 121 generates a first transfer signal 121T and a first output signal 121P according to the sample signal 112. The second stage of sub-converting unit 122 generates a second transfer signal 122T and a second output signal 122P according to the sample signal 121P. Similarly, the (N−1)-th stage of sub-converting unit 12N generates an (N−1)-th transfer signal 12NT and an output signal 12NP according to a previous stage of output signal, wherein (N−1) is a positive integer greater than 1. The N-th stage of sub-converting unit generates an N-th transfer signal 129T only according to a previous stage of output signal. Finally, the delay digital correction module 13 properly corrects each stage of transfer signal 121T to 129T and thus generates a digital signal 131. However, each stage of sub-converting unit of the pipeline analog to digital converter 1 has similar functions, so the stages of sub-converting units may be integrated into a single stage of cyclic pipeline analog to digital converter by way of cyclic design.
As shown in FIG. 2, the conventional cyclic pipeline analog to digital converter 2 includes a sample/hold module 21, a sub-analog/digital converting module 22, a digital/analog converting module 23 and a delay digital correction module 24.
The sample/hold module 21 samples an input signal 211 and generates a sample signal 213 according to the input signal 211 and a residual signal 212. The sub-analog/digital converting module 22 generates a digital conversion signal 221 to 223 according to the sample signal 213. The digital/analog converting module 23 firstly receives the sample signal 213, and then decides to receive reference signals 251 to 253 according to the digital conversion signals 221 to 223, respectively. Finally, the updated residual signal 212 is generated, and the sample/hold module 21 updates the sample signal 213 according to the updated residual signal 212 in the cyclic processing manner until the designed cyclic number of the converter 2 is reached. Then, the delay digital correction module 24 properly corrects the digital conversion signals 221 to 223, which are generated at different time during the cyclic process, and thus generates a digital signal 241.
Referring to FIG. 3, the digital/analog converting module 23 includes a plurality of switches 231 to 236, a capacitor 237, a capacitor 238 and an amplifier 239. The switches 234 and 235 are simultaneously ON to make the capacitors 237 and 238 receive the sample signal 213 and be charged, respectively. At this time, the switches 231 to 233 and the switch 236 are OFF. Then, the switches 234 and 235 are simultaneously OFF to make the capacitors 237 and 238 output a transfer signal 237A and a transfer signal 238A to the amplifier 239, respectively. Meanwhile, one of the switches 231 to 233 and the switch 236 are simultaneously ON to make the amplifier 239 and the capacitor 238 become a feedback circuit. At this time, the switches 231 to 233 are decided to be ON to input one of the reference signals 251 to 253 to the capacitor 237 and to charge the capacitor 237 according to the digital conversion signals 221 to 223, respectively. The amplifier 239 generates the residual signal 212 according to the transfer signals 237A and 238A. At this time, the voltage relationship among the feedback signal of the amplifier 239 and the capacitor 238, the sample signal 213 and one of the reference signals 251 to 253 is described by Equation 1:
                              V          feedback                =                                            (                                                                    C                    237                                    +                                      C                    238                                                                    C                  238                                            )                        ⁢                          V              213                                +                                    (                                                C                  237                                                  C                  238                                            )                        ⁢                          V              25                                                          (                  Equation          ⁢                                          ⁢          1                )            
Wherein, Vfeedback is the voltage of the feedback signal, V213 is the voltage of the sample signal 213, V25 is the voltage of one of the reference signals 251 to 253, C237 and C238 are capacitances of the capacitor 237 and the capacitor 238, respectively, and the voltage of the residual signal 212 is the same as the voltage Vfeedback of the feedback signal.
The cyclic pipeline analog to digital converter 2 can rapidly convert an analog signal into a digital signal. As shown in Equation 1, however, the matching between the capacitor 237 and the capacitor 238 may influence the generation of the residual signal 212, the residual signal 212 may influence the generation of the sample signal 213, the sample signal 213 may influence the processing results of the sub-analog/digital converting module 22 and the digital/analog converting module 23, and then influence the residual signal 212 in the digital/analog converting module 23. Such a vicious circle deteriorates the precision of the converter 2.
Consequently, it is an important subject of the invention to provide a cyclic pipeline analog to digital converter in order to ease the influence of the element matching in the digital/analog converting module, and thus enhance the precision of the analog to digital converter.